IP核调用

陆判4599

# ** Note: (vsim-3812) Design is being optimized...
# ** Error: D:/APP/Fire/pll/quartus_prj/../sim/tb_pll.v(14): Module 'pll' is not defined.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./pll_ip_run_msim_rtl_verilog.do PAUSED at line 41